82801FB Datasheet, PDF (534/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
14.1.16
PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F7)
Address Offset: 50h
Default Value: 01h
Attribute: RO
Size:
8 bits
Bit
Description
7:0
Power Management Capability ID — RO. A value of 01h indicates that this is a PCI Power
Management capabilities field.
14.1.17
NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F7)
Address Offset: 51h
Default Value: 58h
Attribute: R/W (special)
Size:
8 bits
Bit
Description
Next Item Pointer 1 Value — R/W (special). This register defaults to 58h, which indicates that the
next capability registers begin at configuration offset 58h. This register is writable when the
WRT_RDONLY bit (D29:F7:80h, bit 0) is set. This allows BIOS to effectively hide the Debug Port
7:0 capability registers, if necessary. This register should only be written during system initialization
before the plug-and-play software has enabled any master-initiated traffic. Only values of 58h
(Debug Port visible) and 00h (Debug Port invisible) are expected to be programmed in this register.
NOTE: Register not reset by D3-to-D0 warm reset.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet