82801FB Datasheet, PDF (116/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.5
LPC Bridge (w/ System and Management Functions)
(D31:F0)
The LPC bridge function of the ICH6 resides in PCI Device 31:Function 0. In addition to the LPC
bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers,
Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and
functions associated with other functional units (power management, GPIO, USB, IDE, etc.) are
described in their respective sections.
5.5.1 LPC Interface
The ICH6 implements an LPC interface as described in the Low Pin Count Interface Specification,
Revision 1.1. The LPC interface to the ICH6 is shown in Figure 5-3. Note that the ICH6
implements all of the signals that are shown as optional, but peripherals are not required to do so.
Figure 5-3. LPC Interface Diagram
PCI Bus
Intel^® ICH6
LAD[3:0]
LFRAME#
LDRQ#
(optional)
SUS_STAT#
LPCPD#
(optional)
GPI
LSMI#
(optional)
PCI
PCI
CLK RST#
PCI
PCI
SERIRQ ^PME#
LPC Device
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet