82801FB Datasheet, PDF (165/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
power cycle expires, the Power Button must be pressed for another 4 to 5 seconds to create the
Override condition to S5.
Sleep Button
The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button.
It differs from the power button in that it only is a request to go from S0 to S1–S4 (not S5). Also, in
an S5 state, the Power Button can wake the system, but the Sleep Button cannot.
Although the ICH6 does not include a specific signal designated as a Sleep Button, one of the
GPIO signals can be used to create a “Control Method” Sleep Button. See the Advanced
Configuration and Power Interface, Version 2.0b for implementation details.
5.14.9.2 RI# (Ring Indicator)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-34 shows
when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the ICH6
generates an interrupt based on RI# active, and the interrupt will be set up as a Break event.
Table 5-34. Transitions Due to RI# Signal
Present State
S0
S1–S5
Event
RI# Active
RI# Active
RI_EN
X
0
1
Event
Ignored
Ignored
Wake Event
Note: Filtering/Debounce on RI# will not be done in ICH6. Can be in modem or external.
5.14.9.3
PME# (PCI Power Management Event)
The PME# signal comes from a PCI device to request that the system be restarted. The PME#
signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME#
signal goes from high to low. No event is caused when it goes from low to high.
There is also an internal PME_B0 bit. This is separate from the external PME# signal and can
cause the same effect.
5.14.9.4
SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the ICH6
attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. If the
SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter
starts. If at any point during the count the SMBus goes idle the reset occurs. If, however, the
counter expires and the SMBus is still active, a reset is forced upon the system even though activity
is still occurring.
Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYSRESET#
input remains asserted or not. It cannot occur again until SYS_RESET# has been detected inactive
after the debounce logic, and the system is back to a full S0 state with PLTRST# inactive. Note that
if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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