82801FB Datasheet, PDF (480/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.41
.
ATS—APM Trapping Status Register (SATA–D31:F2)
Address Offset: C4h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Bit
Description
7:4 Reserved
3
Secondary Slave Trap (SST) — R/WC. This bit indicates that a trap occurred to the secondary
slave device.
2
Secondary Master Trap (SPT) — R/WC. This bit indicates that a trap occurred to the secondary
master device.
1
Primary Slave Trap (PST) — R/WC. This bit indicates that a trap occurred to the primary slave
device.
0
Primary Master Trap (PMT) — R/WC. This bit indicates that a trap occurred to the primary master
device.
12.1.42
.
SP—Scratch Pad Register (SATA–D31:F2)
Address Offset: D0h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
Data (DT) — R/W. This is a read/write register that is available for software to use. No hardware
action is taken on this register.
12.1.43 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)
Address Offset: E0h–E3h
Default Value: 00000000h
Attribute:
Size:
R/W, R/WC
32 bits
Bits
Description
31:14 Reserved
Port 3 BIST FIS Initiate (P3BFI) — R/W. When a rising edge is detected on this bit field, the ICH6
initiates a BIST FIS to the device on Port 3, using the parameters specified in this register and the
13
(Desktop
Only)
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 3 is
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P3BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
13
(Mobile Reserved.
Only)
Port 2 BIST FIS Initiate (P2BFI) — R/W. When a rising edge is detected on this bit field, the ICH6
initiates a BIST FIS to the device on Port 2, using the parameters specified in this register and the
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 2 is
12
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH6 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P2BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet