82801FB Datasheet, PDF (779/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

24 Testability
Testability
24.1 XOR Chain Test Mode Description
The Intel^® ICH6 supports XOR Chain test mode. This non-functional test mode is a dedicated test
mode when the chip is not operating in its normal manner. The XOR Chain Mode is entered as
indicated in the following figure:
Figure 24-1. XOR Chain Test Mode Selection, Entry and Testing
PCICLK
RSMRST# /
LAN_RST#
XOR Chain Test Mode Selection, Entry and Testing
5ms 10ms
Run 120 ms Run 2 ms
See Note on
Chain 4
Option
RTCRST#
PWROK
REQ[4:1]#
ACZ_SDOUT /
EE_DOUT
Chain Select (1-5)
TP3 / GPIO25
DMI_CLK
Held Low
DMI_CLKp = ‘0’
DMI_CLKn = ‘1’
Toggle
XOR Output Enabled
Notes: RSMRST#, PWROK, RTCRST#, LAN_RST# must be held high during test mode and output testing.
PCICLK & DMI_CLK should be approximately 1 MHz while running/toggling
Chain 4 Combination Option:
If LAN_RST# = 0 during testing (XOR Output Enabled) then Chains 4-1 and 4-2 are separate.
If LAN_RST# = 1 during testing then Chains 4-1 and 4-2 are combined with output on PLTRST#.
LAN_RST# must be high for all other chains
For chains 4 and 5, all PETx[n] signals (of that chain) must be driven during testing.
REQ# Settings
REQ[4:1]# = 0000
REQ[4:1]# = 0001
REQ[4:1]# = 0010
REQ[4:1]# = 0011
REQ[4:1]# = 0100
XOR Chain
XOR 1
XOR 2
XOR 3
XOR 4
XOR 5
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
779