82801FB Datasheet, PDF (680/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.4
PCISTS—PCI Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 06–07h
Default Value: 0010h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
Detected Parity Error (DPE) — R/WC.
15 ^{0 = No parity error detected.}
1 = Set when the root port receives a command or data from the backbone with a parity error. This
is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.
Signaled System Error (SSE) — R/WC.
14 _{0 = No system error signaled.}
1 = Set when the root port signals a system error to the internal SERR# logic.
Received Master Abort (RMA) — R/WC.
13 ^{0 = Root port has not received a completion with unsupported request status from the backbone.}
1 = Set when the root port receives a completion with unsupported request status from the
backbone.
Received Target Abort (RTA) — R/WC.
12 _{0 = Root port has not received a completion with completer abort from the backbone.}
1 = Set when the root port receives a completion with completer abort from the backbone.
Signaled Target Abort (STA) — R/WC.
11 ^{0 = No target abort received.}
1 = Set whenever the root port forwards a target abort received from the downstream device onto
the backbone.
10:9 DEVSEL# Timing Status (DEV_STS) — Reserved per the PCI Express* Base Specification.
Master Data Parity Error Detected (DPED) — R/WC.
8 ^{0 = No data parity error received.}
1 = Set when the root port receives a completion with a data parity error on the backbone and
PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.
7 Fast Back to Back Capable (FB2BC) — Reserved per the PCI Express* Base Specification.
6 Reserved
5 66 MHz Capable — Reserved per the PCI Express* Base Specification.
4 Capabilities List — RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status — RO. Indicates status of Hot-Plug and power management interrupts on the root
port that result in INTx# message generation.
3
0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of
PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3:04h:bit 10).
2:0 Reserved
680
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet