82801FB Datasheet, PDF (568/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.1.14
HOSTC—Host Configuration Register (SMBus—D31:F3)
Address Offset: 40h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:3 Reserved
I²C_EN — R/W.
2
0 = SMBus behavior.
1 = The ICH6 is enabled to communicate with I²C devices. This will change the formatting of some
commands.
SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1 _{1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to}
Section 5.21.4 (Interrupts / SMI#).
This bit needs to be set for SMBALERT# to be enabled.
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
0
1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit
(offset SMBASE + 02h, bit 0) needs to be enabled for the SMB Host controller to interrupt or
SMI#. Note that the SMB Host controller will not respond to any new requests until all interrupt
requests have been cleared.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet