82801FB Datasheet, PDF (399/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.1.5
C4-TIMING_CNT—C4 Timing Control Register
(PM—D31:F0) (Mobile Only)
Offset Address:
Default Value:
Lockable:
Power Well:
AAh
00h
No
Core
Attribute:
Size:
Usage:
This register is used to enable C-state related modes.
R/W
8-bit
ACPI, Legacy
Bit
Description
7:4 Reserved
DPRSLPVR to STPCPU — R/W. This field selects the amount of time that the ICH6 waits for from
the de-assertion of DPRSLPVR to the de-assertion of STP_CPU#. This provides a programmable
time for the processor’s voltage to stabilize when exiting from a C4 state. This thus changes the
value for t266.
3:2
Bits
t266_min
t266_max
Comment
00b
95 µs
101 µs Default
01b
22 µs
28 µs
Value used for “Fast”
VRMs
10b
Reserved
11b
Reserved
DPSLP-TO-SLP — R/W. This field selects the DPSLP# de-assertion to CPU_SLP# de-assertion
time (t270). Normally this value is determined by the CPU_PLL_LOCK_TIME field in the
GEN_PMCON_2 register. When this field is non-zero, then the values in this register have higher
priority. It is software’s responsibility to program these fields in a consistent manner.
Bits
t270
1:0
Use value is
00b CPU_PLL_LOCK_TIME
field (default is 30 µs)
01b 20 µs
10b 15 µs
11b 10 µs
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
399