82801FB Datasheet, PDF (440/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.4 PCISTS — PCI Status Register (IDE—D31:F1)
Address Offset: 06–07h
Default Value: 0280h
Attribute: R/WC, RO
Size:
16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
effect.
Bit
Description
15 Detected Parity Error (DPE) — RO. Reserved as 0.
14 Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
13 _{0 = Master abort Not generated by Bus Master IDE interface function.}
1 = Bus Master IDE interface function, as a master, generated a master abort.
12 Reserved as 0 — RO.
11 Reserved as 0 — RO.
DEVSEL# Timing Status (DEV_STS) — RO.
10:9 _{01 = Hardwired; however, the ICH6 does not have a real DEVSEL# signal associated with the IDE}
unit, so these bits have no effect.
8 Data Parity Error Detected (DPED) — RO. Reserved as 0.
7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
6 User Definable Features (UDF) — RO. Reserved as 0.
5 66MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
4 Reserved
Interrupt Status (INTS) — RO. This bit is independent of the state of the Interrupt Disable bit in the
command register.
3
0 = Interrupt is cleared.
1 = Interrupt/MSI is asserted.
NOTE: This bit will read ‘1’ after Power On Reset when no parallel ATA drive is attached. This is
the intended behavior.
2:0 Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet