82801FB Datasheet, PDF (608/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

AC ’97 Modem Controller Registers (D30:F3)
17.1.1
17.1.2
17.1.3
VID—Vendor Identification Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
00–01h
8086
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0 Vendor ID.
Description
DID—Device Identification Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
02–03h
266Dh
No
Attribute:
Size:
Power Well:
RO
16 Bits
Core
Bit
15:0 Device ID.
Description
PCICMD—PCI Command Register (Modem—D30:F3)
Address Offset:
Default Value:
Lockable:
04–05h
0000h
No
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
PCICMD is a 16-bit control register. Refer to the PCI Local Bus Specification for complete details
on each bit.
Bit
15:11
10
9
8
7
6
5
4
3
2
1
0
Description
Reserved. Read 0.
Interrupt Disable (ID)— R/W.
0 = The INTx# signals may be asserted and MSIs may be generated.
1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate MSIs.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. This bit controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — RO. Hardwired to 0, AC ‘97 does not respond to memory
accesses.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable access. (default = 0).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet