82801FB Datasheet, PDF (283/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.1.3
PCICMD—PCI Command Register
(LAN Controller—B1:D8:F0)
Offset Address: 04–05h
Default Value: 0000h
Attribute:
Size:
RO, R/W
16 bits
Bit
Description
15:11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = Enable.
1 = Disables LAN controller to assert its INTA signal.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0. The integrated LAN controller will not run
fast back-to-back PCI cycles.
SERR# Enable (SERR_EN) — R/W.
0 = Disable.
1 = Enable. Allow SERR# to be asserted.
Wait Cycle Control (WCC) — RO. Hardwired to 0. Not implemented.
Parity Error Response (PER) — R/W.
0 = The LAN controller will ignore PCI parity errors.
1 = The integrated LAN controller will take normal action when a PCI parity error is detected and
will enable generation of parity on DMI.
VGA Palette Snoop (VPS) — RO. Hardwired to 0. Not Implemented.
Memory Write and Invalidate Enable (MWIE) — R/W.
0 = Disable. The LAN controller will not use the Memory Write and Invalidate command.
1 = Enable.
Special Cycle Enable (SCE) — RO. Hardwired to 0. The LAN controller ignores special cycles.
Bus Master Enable (BME) — R/W.
0 = Disable.
1 = Enable. The ICH6’s integrated LAN controller may function as a PCI bus master.
Memory Space Enable (MSE) — R/W.
0 = Disable.
1 = Enable. The ICH6’s integrated LAN controller will respond to the memory space accesses.
I/O Space Enable (IOSE) — R/W.
0 = Disable.
1 = Enable. The ICH6’s integrated LAN controller will respond to the I/O space accesses.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
283