82801FB Datasheet, PDF (62/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
Table 2-8. IDE Interface Signals (Sheet 2 of 2)
Name
Type
Description
DIOR# /
(DWSTB /
RDMARDY#)
DIOW# /
(DSTOP)
IORDY /
(DRSTB /
WDMARDY#)
Disk I/O Read (PIO and Non-Ultra DMA): This is the command to the IDE device
that it may drive data onto the DD lines. Data is latched by the ICH6 on the de-
assertion edge of DIOR#. The IDE device is selected either by the ATA register file
chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge
(DDAK#).
O Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write strobe for writes
to disk. When writing to disk, ICH6 drives valid data on rising and falling edges of
DWSTB.
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA ready for reads
from disk. When reading from disk, ICH6 de-asserts RDMARDY# to pause burst
data transfers.
Disk I/O Write (PIO and Non-Ultra DMA): This is the command to the IDE device
that it may latch data from the DD lines. Data is latched by the IDE device on the
de-assertion edge of DIOW#. The IDE device is selected either by the ATA register
O _{file chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA acknowledge}
(DDAK#).
Disk Stop (Ultra DMA): ICH6 asserts this signal to terminate a burst.
I/O Channel Ready (PIO): This signal will keep the strobe active (DIOR# on reads,
DIOW# on writes) longer than the minimum width. It adds wait-states to PIO
transfers.
I Disk Read Strobe (Ultra DMA Reads from Disk): When reading from disk, ICH6
latches data on rising and falling edges of this signal from the disk.
Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk, this is de-
asserted by the disk to pause burst data transfers.
2.9
LPC Interface
Table 2-9. LPC Interface Signals
Name
Type
Description
LAD[3:0] /
FWH[3:0]
LFRAME# /
FWH[4]
LDRQ[0]#
LDRQ[1]# /
GPI[41]
I/O
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-ups are
provided.
O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or
bus master access. These signals are typically connected to external Super I/O
I _{device. An internal pull-up resistor is provided on these signals.}
LDRQ[1]# may optionally be used as GPI.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet