82801FB Datasheet, PDF (686/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.17
PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset: 28–2Bh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
31:0
Description
Prefetchable Memory Base Upper Portion (PMBU) — R/W. Upper 32-bits of the prefetchable
address base.
19.1.18
PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset: 2C–2Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
Prefetchable Memory Limit Upper Portion (PMLU) — R/W. Upper 32-bits of the prefetchable
address limit.
19.1.19
CAPP—Capabilities List Pointer Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 34h
Default Value: 40h
Attribute:
Size:
R0
8 bits
Bit
Description
7:0
Capabilities Pointer (PTR) — RO. This field indicates that the pointer for the first entry in the
capabilities list is at 40h in configuration space.
19.1.20
INTR—Interrupt Information Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 3C–3Dh
Default Value: See bit description
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
Interrupt Pin (IPIN) — RO. This field indicates the interrupt pin driven by the root port. At reset, this
register takes on the following values, which reflect the reset state of the D28IP register in chipset
configuration space:
Port
15:8
1
2
3
4
Reset Value
D28IP.P1IP
D28IP.P2IP
D28IP.P3IP
D28IP.P4IP
NOTE: The value that is programmed into D28IP is always reflected in this register.
7:0
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate which interrupt line
(vector) the interrupt is connected to. No hardware action is taken on this register.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet