82801FB Datasheet, PDF (575/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.2.9
RCV_SLVA—Receive Slave Address Register
(SMBus—D31:F3)
Register Offset:
Default Value:
Lockable:
SMBASE + 09h
44h
No
Attribute:
Size:
Power Well:
R/W
8 bits
Resume
Bit
Description
7 Reserved
SLAVE_ADDR — R/W. This field is the slave address that the Intel^® ICH6 decodes for read and
6:0
write cycles. the default is not 0, so the SMBus Slave Interface can respond even before the
processor comes up (or if the processor is dead). This register is cleared by RSMRST#, but not by
PLTRST#.
15.2.10
.
SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)
Register Offset:
Default Value:
Lockable:
SMBASE + 0Ah–0Bh
0000h
No
Attribute:
Size:
Power Well:
RO
16 bits
Resume
This register contains the 16-bit data value written by the external SMBus master. The processor
can then read the value from this register. This register is reset by RSMRST#, but not PLTRST#
Bit
Description
15:8 Data Message Byte 1 (DATA_MSG1) — RO. See Section 5.21.7 for a discussion of this field.
7:0 Data Message Byte 0 (DATA_MSG0) — RO. See Section 5.21.7 for a discussion of this field.
15.2.11
.
AUX_STS—Auxiliary Status Register (SMBus—D31:F3)
Register Offset:
Default Value:
Lockable:
SMBASE + 0Ch
00h
No
Attribute:
Size:
Power Well:
R/WC, RO
8 bits
Resume
Bit
Description
7:2 Reserved
SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible mode vs.
Advanced TCO mode.
1
0 = Intel^® ICH6 is in the compatible TCO mode.
1 = ICH6 is in the advanced TCO mode.
CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
0 ^{1 = This bit is set if a received message contained a CRC error. When this bit is set, the DERR bit of}
the host status register will also be set. This bit will be set by the controller if a software abort
occurs in the middle of the CRC portion of the cycle or an abort happens after the ICH6 has
received the final data bit transmitted by an external slave.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
575