82801FB Datasheet, PDF (214/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.21
5.21.1
SMBus Controller (D31:F3)
The ICH6 provides a System Management Bus (SMBus) 2.0 compliant host controller as well as a
SMBus slave interface. The host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). The ICH6 is also capable of operating in a mode
in which it can communicate with I²C compatible devices.
The ICH6 can perform SMBus messages with either packet error checking (PEC) enabled or
disabled. The actual PEC calculation and checking is performed in hardware by the ICH6.
The Slave Interface allows an external master to read from or write to the ICH6. Write cycles can
be used to cause certain events or pass messages, and the read cycles can be used to determine the
state of various status bits. The ICH6’s internal host controller cannot access the ICH6’s internal
Slave Interface.
The ICH6 SMBus logic exists in Device 31:Function 3 configuration space, and consists of a
transmit data path, and host controller. The transmit data path provides the data flow logic needed
to implement the seven different SMBus command protocols and is controlled by the host
controller. The ICH6 SMBus controller logic is clocked by RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller
commands through software, except for the new Host Notify command (which is actually a
received message).
The programming model of the host controller is combined into two portions: a PCI configuration
portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is
done via the PCI configuration space. Real-time programming of the Host interface is done in
system I/O space.
The ICH6 SMBus host controller checks for parity errors as a target. If an error is detected, the
detected parity error bit in the PCI Status Register (Device 31:Function 3:Offset 06h:bit 15) is set.
If bit 6 and bit 8 of the PCI Command Register (Device 31:Function 3:Offset 04h) are set, an
SERR# is generated and the signaled SERR# bit in the PCI Status Register (bit 14) is set.
Unless otherwise specified, all of the SMBus logic and its registers are reset by either RSMRST#
or a similar reset via CF9h.
Host Controller
The SMBus host controller is used to send commands to other SMBus slave devices. Software sets
up the host controller with an address, command, and, for writes, data and optional PEC; and then
tells the controller to start. When the controller has finished transmitting data on writes, or
receiving data on reads, it generates an SMI# or interrupt, if enabled.
The host controller supports eight command protocols of the SMBus interface (see System
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte,
Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block Write–Block Read
Process Call, and Host Notify.
The SMBus host controller requires that the various data and command fields be setup for the type
of command to be sent. When software sets the START bit, the SMBus Host controller performs
the requested transaction, and interrupts the processor (or generates an SMI#) when the transaction
is completed. Once a START command has been issued, the values of the “active registers” (Host
Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet