82801FB Datasheet, PDF (331/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.10
9.1.11
SMLT—Secondary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/W, RO
8 bits
This timer controls the amount of time the ICH6 PCI-to-PCI bridge will burst data on its secondary
interface. The counter starts counting down from the assertion of FRAME#. If the grant is
removed, then the expiration of this counter will result in the de-assertion of FRAME#. If the grant
has not been removed, then the ICH6 PCI-to-PCI bridge may continue ownership of the bus.
Bit
Description
7:3
Master Latency Timer Count (MLTC) — R/W. This 5-bit field indicates the number of PCI clocks, in
8-clock increments, that the ICH6 remains as master of the bus.
2:0 Reserved
IOBASE_LIMIT—I/O Base and Limit Register
(PCI-PCI—D30:F0)
Offset Address: 1C-1Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:12
I/O Limit Address Limit bits[15:12] — R/W. I/O These base address bits corresponding to address
lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
11:8
II/O Limit Address Capability (IOLC) — RO. This field indicates that the bridge does not support 32-
bit I/O addressing.
7:4
I/O Base Address (IOBA) — R/W. These I/O Base address bits corresponding to address lines
15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
3:0
I/O Base Address Capability (IOBC) — RO. This field indicates that the bridge does not support 32-
bit I/O addressing.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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