82801FB Datasheet, PDF (465/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F2)
Address Offset:
Default Value:
Primary: 40–41h
Secondary: 42–43h
0000h
Attribute: R/W
Size:
16 bits
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It
also controls operation of the buffer for PIO transfers.
Note: This register is R/W to maintain software compatibility and enable parallel ATA functionality when
the PCI functions are combined. These bits have no effect on SATA operation unless otherwise
noted.
Bit
Description
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or Secondary decode.
0 = Disable.
1 = Enables the Intel^® ICH6 to decode the associated Command Blocks (1F0–1F7h for primary,
15
170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).
This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
14
13:12
11:10
9:8
7
6
5
NOTE: This bit affects SATA operation in both combined and non-combined ATA modes. See
Section 5.17 for more on ATA modes of operation.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1
IORDY Sample Point (ISP) — R/W. The setting of these bits determines the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved
Recovery Time (RCT) — R/W. The setting of these bits determines the minimum number of PCI
clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
Drive 1 DMA Timing Enable (DTE1) — R/W.
0 = Disable.
1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data
port will run in compatible timing.
Drive 1 Prefetch/Posting Enable (PPE1) — R/W.
0 = Disable.
1 = Enable Prefetch and posting to the IDE data port for this drive.
Drive 1 IORDY Sample Point Enable (IE1) — R/W.
0 = Disable IORDY sampling for this drive.
1 = Enable IORDY sampling for this drive.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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