82801FB Datasheet, PDF (437/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11 IDE Controller Registers (D31:F1)
11.1 PCI Configuration Registers (IDE—D31:F1)
Note: Address locations that are not shown should be treated as Reserved (See Section 6.2 for details).
All of the IDE registers are in the core well. None of the registers can be locked.
Table 11-1. IDE Controller PCI Register Address Map (IDE-D31:F1)
Offset
00–01h
02–03h
04–05h
06–07h
Mnemonic
VID
DID
PCICMD
PCISTS
Register Name
Vendor Identification
Device Identification
PCI Command
PCI Status
08h
RID
Revision Identification
09h
0Ah
0Bh
0Ch
0Dh
10–13h
14–17h
18–1Bh
1C–1Fh
20–23h
2C–2Dh
2E–2Fh
PI
SCC
BCC
CLS
PMLT
PCMD_BAR
PCNL_BAR
SCMD_BAR
SCNL_BAR
BM_BASE
IDE_SVID
IDE_SID
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Primary Master Latency Timer
Primary Command Block Base Address
Primary Control Block Base Address
Secondary Command Block Base Address
Secondary Control Block Base Address
Bus Master Base Address
Subsystem Vendor ID
Subsystem ID
3C
INTR_LN Interrupt Line
3D
40–41h
42–43h
44h
48h
4A–4Bh
54h
C0h
C4h
INTR_PN Interrupt Pin
IDE_TIMP Primary IDE Timing
IDE_TIMS Secondary IDE Timing
SLV_IDETIM Slave IDE Timing
SDMA_CNT Synchronous DMA Control
SDMA_TIM Synchronous DMA Timing
IDE_CONFIG IDE I/O Configuration
ATC
APM Trapping Control
ATS
APM Trapping Status
Default
8086h
266Fh
00h
0280h
See register
description.
8Ah
01h
01h
00h
00h
00000001h
00000001h
00000001h
00000001h
00000001h
00h
0000h
See register
description.
01h
0000h
0000h
00h
00h
0000h
00000000h
00h
00h
Type
RO
RO
R/W, RO
R/W, RO
RO
R/W, RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/WO
R/WO
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/WC
NOTE: The ICH6 IDE controller is not arbitrated as a PCI device; therefore, it does not need a master latency
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
437