82801FB Datasheet, PDF (439/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.3
PCICMD—PCI Command Register (IDE—D31:F1)
Address Offset: 04h–05h
Default Value: 00h
Attribute: RO, R/W
Size:
16 bits
Bit
Description
15:11
10
9
8
7
6
5
4
3
2
1
Reserved
Interrupt Disable (ID) — R/W.
0 = Enables the IDE controller to assert INTA# (native mode) or IRQ14/15 (legacy mode).
1 = Disable. The interrupt will be de-asserted.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — RO. Reserved as 0.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. Controls the ICH6’s ability to act as a PCI master for IDE Bus
Master transfers.
Memory Space Enable (MSE) — R/W.
0 = Disables access.
1 = Enables access to the IDE Expansion memory range. The EXBAR register (Offset 24h) must
be programmed before this bit is set.
NOTE: BIOS should set this bit to a 1.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
Bus Master I/O registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
0 ^NOTES:
1. Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently
disable the Primary or Secondary I/O spaces.
2. When this bit is 0 and the IDE controller is in Native Mode, the Interrupt Pin Register (see
Section 11.1.19) will be masked (the interrupt will not be asserted).
If an interrupt occurs while the masking is in place and the interrupt is still active when the
masking ends, the interrupt will be allowed to be asserted.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
439