82801FB Datasheet, PDF (194/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3)
The ICH6 contains four USB 2.0 full/low-speed host controllers that support the standard
Universal Host Controller Interface (UHCI), Revision 1.1. Each UHCI Host Controller (UHC)
includes a root hub with two separate USB ports each, for a total of eight USB ports.
• Overcurrent detection on all eight USB ports is supported. The overcurrent inputs are not 5 V
tolerant, and can be used as GPIs if not needed.
• The ICH6’s UHCI host controllers are arbitrated differently than standard PCI devices to
improve arbitration latency.
• The UHCI controllers use the Analog Front End (AFE) embedded cell that allows support for
USB full-speed signaling rates, instead of USB I/O buffers.
5.19.1
Data Structures in Main Memory
Section 3.1 - 3.3 of the Universal Host Controller Interface, Revision 1.1 specification details the
data structures used to communicate control, status, and data between software and the ICH6.
5.19.2
Data Transfers to/from Main Memory
Section 3.4 of the Universal Host Controller Interface, Revision 1.1 specification describes the
details on how HCD and the ICH6 communicate via the Schedule data structures.
5.19.3
Data Encoding and Bit Stuffing
The ICH6 USB employs NRZI data encoding (Non-Return to Zero Inverted) when transmitting
packets. Full details on this implementation are given in the Universal Serial Bus Revision 2.0
Specification.
5.19.4 Bus Protocol
5.19.4.1
5.19.4.2
Bit Ordering
Bits are sent out onto the bus least significant bit (LSb) first, followed by next LSb, through to the
most significant bit (MSb) last.
SYNC Field
All packets begin with a synchronization (SYNC) field, which is a coded sequence that generates a
maximum edge transition density. The SYNC field appears on the bus as IDLE followed by the
binary string “KJKJKJKK,” in its NRZI encoding. It is used by the input circuitry to align
incoming data with the local clock and is defined to be 8 bits in length. SYNC serves only as a
synchronization mechanism and is not shown in the following packet diagrams. The last two bits in
the SYNC field are a marker that is used to identify the first bit of the PID. All subsequent bits in
the packet must be indexed from this point.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet