82801FB Datasheet, PDF (451/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.26
ATC—APM Trapping Control Register (IDE—D31:F1)
Address Offset: C0h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved
1
Slave Trap (PST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to
1F0h–1F7h and 3F6h. The active device must be the slave device for the trap and/or SMI# to occur.
0
Master Trap (PMT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to
1F0h–1F7h and 3F6h. The active device must be master device for the trap and/or SMI# to occur.
11.1.27
ATS—APM Trapping Status Register (IDE—D31:F1)
Address Offset: C4h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Bit
Description
7:2 Reserved
1 Slave Trap Status (PSTS) — R/WC. This bit indicates that a trap occurred to the slave device
0 Master Trap Status (PMTS) — R/WC. This bit indicates that a trap occurred to the master device
11.2 Bus Master IDE I/O Registers (IDE—D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located
in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers
can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an
indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be
attempted). The description of the I/O registers is shown in Table 11-2.
Table 11-2. Bus Master IDE I/O Registers
BMIBASE
+ Offset
00
01
02
03
04–07
Mnemonic
BMICP
—
BMISP
—
BMIDP
Register Name
Bus Master IDE Command Primary
Reserved
Bus Master IDE Status Primary
Reserved
Bus Master IDE Descriptor Table Pointer Primary
Default
00h
00h
00h
00h
xxxxxxxxh
Type
R/W
RO
R/WC
RO
R/W
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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