82801FB Datasheet, PDF (644/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.1.35
PVCCAP1—Port VC Capability Register 1
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 104h
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:12
11:10
9:8
7
6:4
3
2:0
Reserved.
Port Arbitration Table Entry Size — RO. Hardwired to 0 since this is an endpoint device.
Reference Clock — RO. Hardwired to 0 since this is an endpoint device.
Reserved.
Low Priority Extended VC Count — RO. Hardwired to 0. Indicates that only VC0 belongs to the low
priority VC group
Reserved.
Extended VC Count — RO. Hardwired to 001b. Indicates that 1 extended VC (in addition to VC0) is
supported by the Intel High Definition Audio controller.
18.1.36
PVCCAP2—Port VC Capability Register 2
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 108h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24
23:8
7:0
VC Arbitration Table Offset — RO. Hardwired to 0 indicating that a VC arbitration table is not
present.
Reserved.
VC Arbitration Capability — RO. Hardwired to 0. These bits are not applicable since the Intel High
Definition Audio controller reports a 0 in the Low Priority Extended VC Count bits in the PVCCAP1
register.
18.1.37
PVCCTL—Port VC Control Register
(Intel^® High Definition Audio Controller—D27:F0)
Address Offset: 10Ch
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:4 Reserved.
VC Arbitration Select — RO. Hardwired to 0. Normally these bits are R/W. However, these bits are
3:1 not applicable since the Intel High Definition Audio controller reports a 0 in the Low Priority Extended
VC Count bits in the PVCCAP1 register
0 Load VC Arbitration Table — RO. Hardwired to 0 since an arbitration table is not present.
644
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet