82801FB Datasheet, PDF (388/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.6.2.2
RTC_REGB—Register B (General Configuration)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0Bh
U0U00UUU (U: Undefined)
No
Attribute:
Size:
Power Well:
R/W
8-bit
RTC
Bit
Description
Update Cycle Inhibit (SET) — R/W. This bit enables/Inhibits the update cycles. This bit is not
affected by RSMRST# nor any other reset signal.
0 = Update cycle occurs normally once each second.
7 ^{1 = A current update cycle will abort and subsequent update cycles will not occur until SET is}
returned to 0. When set is one, the BIOS may initialize time and calendar bytes safely.
NOTE: This bit should be set then cleared early in BIOS POST after each powerup directly after
coin-cell battery insertion.
Periodic Interrupt Enable (PIE) — R/W. This bit is cleared by RSMRST#, but not on any other
reset.
6
0 = Disable.
1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register A.
Alarm Interrupt Enable (AIE) — R/W. This bit is cleared by RTCRST#, but not on any other reset.
5 ^{0 = Disable.}
1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the update
cycle. An alarm can occur once a second, one an hour, once a day, or one a month.
Update-Ended Interrupt Enable (UIE) — R/W. This bit is cleared by RSMRST#, but not on any
other reset.
4
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
Square Wave Enable (SQWE) — R/W. This bit serves no function in the ICH6. It is left in this
3 register bank to provide compatibility with the Motorola 146818B. The ICH6 has no SQW pin. This
bit is cleared by RSMRST#, but not on any other reset.
Data Mode (DM) — R/W. This bit specifies either binary or BCD data representation. This bit is not
affected by RSMRST# nor any other reset signal.
2
0 = BCD
1 = Binary
Hour Format (HOURFORM) — R/W. This bit indicates the hour byte format. This bit is not affected
by RSMRST# nor any other reset signal.
1
0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and PM as one.
1 = Twenty-four hour mode.
Daylight Savings Enable (DSE) — R/W. This bit triggers two special hour updates per year. The
days for the hour adjustment are those specified in United States federal law as of 1987, which is
different than previous years. This bit is not affected by RSMRST# nor any other reset signal.
0 ^{0 = Daylight Savings Time updates do not occur.}
1 = a) Update on the first Sunday in April, where time increments from 1:59:59 AM to 3:00:00 AM.
b) Update on the last Sunday in October when the time first reaches 1:59:59 AM, it is changed
to 1:00:00 AM. The time must increment normally for at least two update cycles (seconds)
previous to these conditions for the time change to occur properly.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet