82801FB Datasheet, PDF (574/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.2.7
15.2.8
Host_BLOCK_DB—Host Block Data Byte Register
(SMBus—D31:F3)
Register Offset: SMBASE + 07h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
Block Data (BDTA) — R/W. This is either a register, or a pointer into a 32-byte block array,
depending upon whether the E32B bit is set in the Auxiliary Control register. When the E32B bit
(offset SMBASE + 0Dh, bit 1) is cleared, this is a register containing a byte of data to be sent on a
block write or read from on a block read, just as it behaved on the ICH3.
When the E32B bit is set, reads and writes to this register are used to access the 32-byte block data
storage array. An internal index pointer is used to address the array, which is reset to 0 by reading
the HCTL register (offset 02h). The index pointer then increments automatically upon each access
to this register. The transfer of block data into (read) or out of (write) this storage array during an
SMBus transaction always starts at index address 0.
When the E2B bit is set, for writes, software will write up to 32-bytes to this register as part of the
setup for the command. After the Host controller has sent the Address, Command, and Byte Count
7:0 ^{fields, it will send the bytes in the SRAM pointed to by this register.}
When the E2B bit is cleared for writes, software will place a single byte in this register. After the host
controller has sent the address, command, and byte count fields, it will send the byte in this register.
If there is more data to send, software will write the next series of bytes to the SRAM pointed to by
this register and clear the DONE_STS bit. The controller will then send the next byte. During the
time between the last byte being transmitted to the next byte being transmitted, the controller will
insert wait-states on the interface.
When the E2B bit is set for reads, after receiving the byte count into the Data0 register, the first
series of data bytes go into the SRAM pointed to by this register. If the byte count has been
exhausted or the 32-byte SRAM has been filled, the controller will generate an SMI# or interrupt
(depending on configuration) and set the DONE_STS bit. Software will then read the data. During
the time between when the last byte is read from the SRAM to when the DONE_STS bit is cleared,
the controller will insert wait-states on the interface.
PEC—Packet Error Check (PEC) Register
(SMBus—D31:F3)
Register Offset: SMBASE + 08h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
PEC_DATA — R/W. This 8-bit register is written with the 8-bit CRC value that is used as the SMBus
PEC data prior to a write transaction. For read transactions, the PEC data is loaded from the SMBus
7:0 into this register and is then read by software. Software must ensure that the INUSE_STS bit is
properly maintained to avoid having this field over-written by a write transaction following a read
transaction.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet