82801FB Datasheet, PDF (177/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5. After step 4 (power button override), if the user presses the power button again, the system
should wake to an S0 state and the processor should start executing the BIOS.
6. If step 5 (power button press) is successful in waking the system, the ICH6 continues sending
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
7. If step 5 (power button press) is unsuccessful in waking the system, the ICH6 continues
sending heartbeats. The ICH6 does not attempt to reboot the system again until some external
intervention occurs (reset, power failure, etc.). (See note 3)
8. After step 3 (third timeout), if a reset is attempted (using a button that pulses PWROK low or
via the message on the SMBus slave I/F), the ICH6 attempts to reset the system.
9. If step 8 (reset attempt) is successful, the BIOS is run. The ICH6 continues sending heartbeats
until the BIOS clears the SECOND_TO_STS bit. (See note 2)
10. If step 8 (reset attempt), is unsuccessful, the ICH6 continues sending heartbeats. The ICH6
does not attempt to reboot the system again without external intervention. Note: A system that
has locked up and can not be restarted with power button press is probably broken (bad power
supply, short circuit on some bus, etc.)
11. This and the following rules/steps apply if the user intervention (power button press, reset,
SMBus message, etc.) occur prior to the third timeout of the watchdog timer.
12. After step 1 (second timeout), if the user does a Power Button Override, the system goes to an
S5 state. The ICH6 continues sending heartbeats at this point.
13. After step 12 (power button override), if the user presses the power button again, the system
should wake to an S0 state and the processor should start executing the BIOS.
14. If step 13 (power button press) is successful in waking the system, the ICH6 continues sending
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
15. If step 13 (power button press) is unsuccessful in waking the system, the ICH6 continues
sending heartbeats. The ICH6 does not attempt to reboot the system again until some external
intervention occurs (reset, power failure, etc.). (See note 3)
16. After step 1 (second timeout), if a reset is attempted (using a button that pulses PWROK low
or via the message on the SMBus slave I/F), the ICH6 attempts to reset the system.
17. If step 16 (reset attempt) is successful, the BIOS is run. The ICH6 continues sending
heartbeats until the BIOS clears the SECOND_TO_STS bit. (See note 2)
18. If step 16 (reset attempt), is unsuccessful, the ICH6 continues sending heartbeats. The ICH6
does not attempt to reboot the system again without external intervention. (See note 3)
If the system is in a G1 (S1–S4) state, the ICH6 sends a heartbeat message every 30–32 seconds. If
an event occurs prior to the system being shutdown, the ICH6 immediately sends an event message
with the next incremented sequence number. After the event message, the ICH6 resumes sending
heartbeat messages.
Note:
Notes for previous two numbered lists.
1. Normally, the ICH6 does not send heartbeat messages while in the G0 state (except in the case
of a lockup). However, if a hardware event (or heartbeat) occurs just as the system is
transitioning into a G0 state, the hardware continues to send the message even though the
system is in a G0 state (and the status bits may indicate this).
These messages are sent via the SMBus. The ICH6 abides by the SMBus rules associated with
collision detection. It delays starting a message until the bus is idle, and detects collisions. If a
collision is detected the ICH6 waits until the bus is idle, and tries again.
2. WARNING: It is important the BIOS clears the SECOND_TO_STS bit, as the alerts interfere
with the LAN device driver from working properly. The alerts reset part of the LAN controller
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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