82801FB Datasheet, PDF (351/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.1.16
PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
PIRQA – 60h, PIRQB – 61h,
PIRQC – 62h, PIRQD – 63h
80h
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
Bit
Description
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in
bits[3:0].
7
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used.
The value of this bit may subsequently be changed by the OS when setting up for I/O
APIC interrupt delivery mode.
6:4 Reserved
IRQ Routing — R/W. (ISA compatible.)
Value
IRQ
0000b Reserved
0001b Reserved
3:0
0010b Reserved
0011b IRQ3
0100b IRQ4
0101b IRQ5
0110b IRQ6
0111b IRQ7
Value
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
IRQ
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved
IRQ14
IRQ15
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
351