82801FB Datasheet, PDF (684/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.14
SSTS—Secondary Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 1E–1Fh
Default Value: 0000h
Attribute:
Size:
R/WC
16 bits
Bit
Description
Detected Parity Error (DPE) — R/WC.
15 _{0 = No error.}
1 = The port received a poisoned TLP.
Received System Error (RSE) — R/WC.
14 _{0 = No error.}
1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device.
Received Master Abort (RMA) — R/WC.
13 _{0 = Unsupported Request not received.}
1 = The port received a completion with “Unsupported Request” status from the device.
Received Target Abort (RTA) — R/WC.
12 _{0 = Completion Abort not received.}
1 = The port received a completion with “Completion Abort” status from the device.
Signaled Target Abort (STA) — R/WC.
11 _{0 = Completion Abort not sent.}
1 = The port generated a completion with “Completion Abort” status to the device.
10:9 Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base Specification.
Data Parity Error Detected (DPD) — R/WC.
0 = Conditions below did not occur.
1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3:3E: bit 0) is set, and either of the following two
8
conditions occurs:
• Port receives completion marked poisoned.
• Port poisons a write request to the secondary side.
7 Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base Specification.
6 Reserved
5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification.
4:0 Reserved
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet