82801FB Datasheet, PDF (397/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.8.1.3
GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address: A4h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, R/WC
8-bit
ACPI, Legacy
RTC
Bit
Description
SWSMI_RATE_SEL — R/W. This field indicates when the SWSMI timer will time out.
Valid values are:
00 = 1.5 ms ± 0.6 ms
7:6 ^{01 = 16 ms ± 4 ms}
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
These bits are not cleared by any type of reset except RTCRST#.
SLP_S4# Minimum Assertion Width — R/W. This field indicates the minimum assertion width of
the SLP_S4# signal to guarantee that the DRAMs have been safely power-cycled.
Valid values are:
11 = 1 to 2 seconds
10 = 2 to 3 seconds
01 = 3 to 4 seconds
5:4 00 = 4 to 5 seconds
This value is used in two ways:
1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to read
when S0 is entered.
2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4# signal from de-
asserting within this minimum time period after asserting.
RTCRST# forces this field to the conservative default state (00b)
SLP_S4# Assertion Stretch Enable — R/W.
3
0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK.
1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this register.
This bit is cleared by RTCRST#
RTC Power Status (RTC_PWR_STS) — R/W. This bit is set when RTCRST# indicates a weak or
2 missing battery. The bit is not cleared by any type of reset. The bit will remain set until the software
clears it by writing a 0 back to this bit position.
Power Failure (PWR_FLR) — R/WC. This bit is in the RTC well, and is not cleared by any type of
reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software
clears this bit by writing a 1 to it.
1 _{1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed.}
NOTE: Clearing CMOS in an ICH-based platform can be done by using a jumper on RTCRST# or
GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by
using a jumper to pull VccRTC low.
AFTERG3_EN — R/W. This bit determines what state to go to when power is re-applied after a
power failure (G3 state). This bit is in the RTC well and is not cleared by any type of reset except
writes to CF9h or RTCRST#.
0 ^{0 = System will return to S0 state (boot) after power is re-applied.}
1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the
S5 state, the only enabled wake event is the Power Button or any enabled wake event that was
preserved through the power failure.
NOTE: Bit will be set when THRMTRIP#-based shutdown occurs.
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock
period may not be detected by the ICH6.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
397