82801FB Datasheet, PDF (669/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.34
SDSTS—Stream Descriptor Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:
Input Stream[0]: HDBAR + 83h
Input Stream[1]: HDBAR + A3h
Input Stream[2]: HDBAR + C3h
Input Stream[3]: HDBAR + E3h
Output Stream[0]: HDBAR + 103h
Output Stream[1]: HDBAR + 123h
Output Stream[2]: HDBAR + 143h
Output Stream[3]: HDBAR + 163h
Default Value: 00h
Attribute:R/WC, RO
Size:
8 bits
Bit
Description
7:6 Reserved.
FIFO Ready (FIFORDY) — RO.
For output streams, the controller hardware will set this bit to 1 while the output DMA FIFO contains
5
enough data to maintain the stream on the link. This bit defaults to 0 on reset because the FIFO is
cleared on a reset.
For input streams, the controller hardware will set this bit to 1 when a valid descriptor is loaded and
the engine is ready for the RUN bit to be set.
Descriptor Error — R/WC. When set, this bit indicates that a serious error occurred during the fetch
of a descriptor. This could be a result of a Master Abort, a parity or ECC error on the bus, or any
other error which renders the current Buffer Descriptor or Buffer Descriptor list useless. This error is
4 ^{treated as a fatal stream error, as the stream cannot continue running. The RUN bit will be cleared}
and the stream will stopped.
Software may attempt to restart the stream engine after addressing the cause of the error and
writing a 1 to this bit to clear it.
FIFO Error — R/WC. This bit is set when a FIFO error occurs. This bit is set even if an interrupt is
not enabled. The bit is cleared by writing a 1 to it.
For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set. When this
3
happens, the FIFO pointers do not increment and the incoming data is not written into the FIFO,
thereby being lost.
For an output stream, this indicates a FIFO underrun when there are still buffers to send. The
hardware should not transmit anything on the link for the associated stream if there is not valid data
to send.
Buffer Completion Interrupt Status — R/WC.
2 ^{This bit is set to 1 by the hardware after the last sample of a buffer has been processed, AND if the}
Interrupt on Completion bit is set in the command byte of the buffer descriptor. It remains active until
software clears it by writing a 1 to it.
1:0 Reserved.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
669