82801FB Datasheet, PDF (296/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LAN Controller Registers (B1:D8:F0)
8.2.2
SCB_CMD—System Control Block Command Word
Register (LAN Controller—B1:D8:F0)
Offset Address: 02–03h
Default Value: 0000h
Attribute:
Size:
R/W, WO
16 bits
The processor places commands for the Command and Receive units in this register. Interrupts are
also acknowledged in this register.
Bit
Description
CX Mask (CX_MSK) — R/W.
15 _{0 = Interrupt not masked.}
1 = Disable the generation of a CX interrupt.
FR Mask (FR_MSK) — R/W.
14 _{0 = Interrupt not masked.}
1 = Disable the generation of an FR interrupt.
CNA Mask (CNA_MSK) — R/W.
13 _{0 = Interrupt not masked.}
1 = Disable the generation of a CNA interrupt.
RNR Mask (RNR_MSK) — R/W.
12 _{0 = Interrupt not masked.}
1 = Disable the generation of an RNR interrupt.
ER Mask (ER_MSK) — R/W.
11 _{0 = Interrupt not masked.}
1 = Disable the generation of an ER interrupt.
FCP Mask (FCP_MSK) — R/W.
10 _{0 = Interrupt not masked.}
1 = Disable the generation of an FCP interrupt.
Software Generated Interrupt (SI) — WO.
9 _{0 = No Effect.}
1 = Setting this bit causes the LAN controller to generate an interrupt.
Interrupt Mask (IM) — R/W. This bit enables or disables the LAN controller’s assertion of the INTA#
signal. This bit has higher precedence that the Specific Interrupt Mask bits and the SI bit.
8
0 = Enable the assertion of INTA#.
1 = Disable the assertion of INTA#.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet