82801FB Datasheet, PDF (660/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Intel^® High Definition Audio Controller Registers (D27:F0)
18.2.14
CORBLBASE—CORB Lower Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 40h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
CORB Lower Base Address — R/W. Lower address of the Command Output Ring Buffer, allowing
31:7 the CORB base address to be assigned on any 128-B boundary. This register field must not be
written when the DMA engine is running or the DMA transfer may be corrupted.
6:0
CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the CORB to be
allocated with 128B granularity to allow for cache line fetch optimizations.
18.2.15
CORBUBASE—CORB Upper Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 44h
Default Value: 00000000h
Attribute:
DWord Size:
R/W
32 bits
Bit
Description
CORB Upper Base Address — R/W. Upper 32 bits of the address of the Command Output Ring
31:0 buffer. This register field must not be written when the DMA engine is running or the DMA transfer
may be corrupted.
18.2.16
CORBRP—CORB Write Pointer Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address: HDBAR + 48h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:8 Reserved.
CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this field in
7:0
DWord granularity. The DMA engine fetches commands from the CORB until the Read Pointer
matches the Write Pointer. Supports 256 CORB entries (256x4B = 1KB). This register field may be
written while the DMA engine is running.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet