82801FB Datasheet, PDF (24/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Contents
14.2.3
14.2.2.2 USB2.0_STS—USB 2.0 Status Register ............................................. 550
14.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register ............................ 552
14.2.2.4 FRINDEX—Frame Index Register ....................................................... 553
14.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment
Register................................................................................................ 554
14.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
Register................................................................................................ 554
14.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
Register................................................................................................ 555
14.2.2.8 CONFIGFLAG—Configure Flag Register ............................................ 555
14.2.2.9 PORTSC—Port N Status and Control Register ................................... 556
USB 2.0-Based Debug Port Register .................................................................. 560
14.2.3.1 CNTL_STS—Control/Status Register.................................................. 560
14.2.3.2 USBPID—USB PIDs Register ............................................................. 562
14.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ................................ 562
14.2.3.4 CONFIG—Configuration Register........................................................ 562
15 SMBus Controller Registers (D31:F3)......................................................................... 563
15.1 PCI Configuration Registers (SMBus—D31:F3)............................................................... 563
15.1.1 VID—Vendor Identification Register (SMBus—D31:F3)...................................... 563
15.1.2 DID—Device Identification Register (SMBus—D31:F3) ...................................... 564
15.1.3 PCICMD—PCI Command Register (SMBus—D31:F3)....................................... 564
15.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) .............................................. 565
15.1.5 RID—Revision Identification Register (SMBus—D31:F3) ................................... 565
15.1.6 PI—Programming Interface Register (SMBus—D31:F3) .................................... 566
15.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)........................................... 566
15.1.8 BCC—Base Class Code Register (SMBus—D31:F3) ......................................... 566
15.1.9 SMB_BASE—SMBus Base Address Register
(SMBus—D31:F3) ............................................................................................... 566
15.1.10 SVID—Subsystem Vendor Identification Register
(SMBus—D31:F2/F4) .......................................................................................... 567
15.1.11 SID—Subsystem Identification Register
(SMBus—D31:F2/F4) .......................................................................................... 567
15.1.12 INT_LN—Interrupt Line Register (SMBus—D31:F3)........................................... 567
15.1.13 INT_PN—Interrupt Pin Register (SMBus—D31:F3) ............................................ 567
15.1.14 HOSTC—Host Configuration Register (SMBus—D31:F3) .................................. 568
15.2 SMBus I/O Registers ........................................................................................................ 569
15.2.1 HST_STS—Host Status Register (SMBus—D31:F3).......................................... 570
15.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)........................................ 571
15.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) .................................. 573
15.2.4 XMIT_SLVA—Transmit Slave Address Register
(SMBus—D31:F3) ............................................................................................... 573
15.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3)............................................ 573
15.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3)............................................ 573
15.2.7 Host_BLOCK_DB—Host Block Data Byte Register
(SMBus—D31:F3) ............................................................................................... 574
15.2.8 PEC—Packet Error Check (PEC) Register
(SMBus—D31:F3) ............................................................................................... 574
15.2.9 RCV_SLVA—Receive Slave Address Register
(SMBus—D31:F3) ............................................................................................... 575
15.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3) .......................... 575
15.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ................................... 575
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet