82801FB Datasheet, PDF (195/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
5.19.4.3
5.19.4.4
5.19.4.5
5.19.4.6
5.19.4.7
Packet Field Formats
All packets have distinct start and end of packet delimiters. Full details are given in the Universal
Serial Bus Revision 2.0 Specification in section 8.3.1.
Address Fields
Function endpoints are addressed using the function address field and the endpoint field. Full
details on this are given in the Universal Serial Bus Revision 2.0 Specification in section 8.3.2.
Frame Number Field
The frame number field is an 11-bit field that is incremented by the host on a per frame basis. The
frame number field rolls over upon reaching its maximum value of 7FFh, and is sent only for SOF
tokens at the start of each frame.
Data Field
The data field may range from 0 to 1023 bytes and must be an integral numbers of bytes. Data bits
within each byte are shifted out LSB first.
Cyclic Redundancy Check (CRC)
CRC is used to protect the all non-PID fields in token and data packets. In this context, these fields
are considered to be protected fields. Full details on this are given in the Universal Serial Bus
Revision 2.0 Specification in section 8.3.5.
5.19.5
Packet Formats
The USB protocol calls out several packet types: token, data, and handshake packets. Full details
on this are given in the Universal Serial Bus Revision 2.0 Specification in section 8.4.
5.19.6
USB Interrupts
There are two general groups of USB interrupt sources, those resulting from execution of
transactions in the schedule, and those resulting from an ICH6 operation error. All
transaction-based sources can be masked by software through the ICH6’s Interrupt Enable register.
Additionally, individual transfer descriptors can be marked to generate an interrupt on completion.
When the ICH6 drives an interrupt for USB, it internally drives the PIRQA# pin for USB
function #0 and USB function #3, PIRQD# pin for USB function #1, and the PIRQC# pin for USB
function #2, until all sources of the interrupt are cleared. In order to accommodate some operating
systems, the Interrupt Pin register must contain a different value for each function of this new
multi-function device.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
195