82801FB Datasheet, PDF (59/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Signal Description
Table 2-6. PCI Interface Signals (Sheet 2 of 3)
Name
TRDY#
STOP#
PAR
PERR#
REQ[0:3]#
REQ[4]# /
GPI[40]
REQ[5]# /
GPI[1]
REQ[6]# /
GPI[0]
GNT[0:3]#
GNT[4]# /
GPO[48]
GNT[5]# /
GPO[17]#
GNT[6]# /
GPO[16]#
PCICLK
PCIRST#
Type
I/O
I/O
I/O
I/O
Description
Target Ready: TRDY# indicates the ICH6's ability as a target to complete the
current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A
data phase is completed when both TRDY# and IRDY# are sampled asserted.
During a read, TRDY# indicates that the ICH6, as a target, has placed valid data on
AD[31:0]. During a write, TRDY# indicates the ICH6, as a target is prepared to
latch data. TRDY# is an input to the ICH6 when the ICH6 is the initiator and an
output from the ICH6 when the ICH6 is a target. TRDY# is tri-stated from the
leading edge of PLTRST#. TRDY# remains tri-stated by the ICH6 until driven by a
target.
Stop: STOP# indicates that the ICH6, as a target, is requesting the initiator to stop
the current transaction. STOP# causes the ICH6, as an initiator, to stop the current
transaction. STOP# is an output when the ICH6 is a target and an input when the
ICH6 is an initiator.
Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,
AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH6 counts the number of
one within the 36 bits plus PAR and the sum is always even. The ICH6 always
calculates PAR on 36 bits regardless of the valid byte enables. The ICH6 generates
PAR for address and data phases and only guarantees PAR to be valid one PCI
clock after the corresponding address or data phase. The ICH6 drives and tri-
states PAR identically to the AD[31:0] lines except that the ICH6 delays PAR by
exactly one PCI clock. PAR is an output during the address phase (delayed one
clock) for all ICH6 initiated transactions. PAR is an output during the data phase
(delayed one clock) when the ICH6 is the initiator of a PCI write transaction, and
when it is the target of a read transaction. ICH6 checks parity when it is the target
of a PCI write transaction. If a parity error is detected, the ICH6 will set the
appropriate internal status bits, and has the option to generate an NMI# or SMI#.
Parity Error: An external PCI device drives PERR# when it receives data that has
a parity error. The ICH6 drives PERR# when it detects a parity error. The ICH6 can
either generate an NMI# or SMI# upon detecting a parity error (either detected
internally or reported via the PERR# signal).
I
PCI Requests: The ICH6 supports up to 7 masters on the PCI bus. The REQ[4]#,
REQ[5]#, and REQ[6]# pins can instead be used as a GPI.
PCI Grants: The ICH6 supports up to 7 masters on the PCI bus. The GNT[4]# pin
can instead be used as a GPO.
Pull-up resistors are not required on these signals. If pull-ups are used, they should
be tied to the Vcc3_3 power rail. GNT[5]#/GPO[17] and GNT[6]#/GPO[17] both
O _{have an internal pull-up.}
NOTE: GNT[6] is sampled at the rising edge of PWROK as a functional strap. See
Section 2.22.1 for more details. There is a weak, integrated pull-up resistor
on the GNT[6] pin.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all transactions on
the PCI Bus.
I
NOTE: (Mobile Only) This clock does not stop based on STP_PCI# signal. PCI
Clock only stops based on SLP_S3#.
PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the
primary interface PLTRST# signal and the state of the Secondary Bus Reset bit of
O the Bridge Control register (D30:F0:3Eh, bit 6).
NOTE: PCIRST# is in the VccSus3_3 well.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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