82801FB Datasheet, PDF (705/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.48
PVC—Port Virtual Channel Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 10C–10Dh
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:4 Reserved.
VC Arbitration Select (AS) — R/W. This field indicates which VC should be programmed in the VC
3:1 arbitration table. The root port takes no action on the setting of this field since there is no arbitration
table.
0
Load VC Arbitration Table (LAT) — R/W. This bit indicates that the table programmed should be
loaded into the VC arbitration table. This bit always returns 0 when read.
19.1.49
PVS — Port Virtual Channel Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 10E–10Fh
Default Value: 0000h
Attribute:
Size:
RO
16 bits
Bit
Description
15:1 Reserved.
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the VC
0 Arbitration table when it is being updated. This field is always 0 in the root port since there is no VC
arbitration table.
19.1.50 V0CAP — Virtual Channel 0 Resource Capability Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset: 110–113h
Default Value: 00000001h
Attribute:
Size:
RO
32 bits
Bit
Description
31:24
23
22:16
15
14
13:8
7:0
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table since the
arbitration is fixed.
Reserved.
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and therefore this field is
not used.
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable transactions.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not just advanced
packet switching transactions.
Reserved.
Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed port arbitration.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
705