82801FB Datasheet, PDF (372/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

LPC Interface Bridge Registers (D31:F0)
10.3.3
Counter Access Ports Register (LPC I/F—D31:F0)
I/O Address:
Default Value:
Counter 0 – 40h,
Counter 1 – 41h,
Counter 2 – 42h
All bits undefined
Attribute:
R/W
Size:
8 bit
Bit
Description
Counter Port — R/W. Each counter port address is used to program the 16-bit Count Register. The
order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval
7:0 Counter Control Register at port 43h. The counter port is also used to read the current count from
the Count Register, and return the status of the counter programming following a Read Back
Command.
10.4 8259 Interrupt Controller (PIC) Registers
(LPC I/F—D31:F0)
10.4.1 Interrupt Controller I/O MAP (LPC I/F—D31:F0)
The interrupt controller registers are located at 20h and 21h for the master controller (IRQ 0–7),
and at A0h and A1h for the slave controller (IRQ 8–13). These registers have multiple functions,
depending upon the data written to them. Table 10-3 shows the different register possibilities for
each address.
Table 10-3. PIC Registers (LPC I/F—D31:F0)
Port
20h
21h
A0h
A1h
4D0h
4D1h
Aliases
24h, 28h,
2Ch, 30h,
34h, 38h, 3Ch
25h, 29h,
2Dh, 31h,
35h, 39h, 3Dh
A4h, A8h,
ACh, B0h,
B4h, B8h, BCh
A5h, A9h,
ADh, B1h,
B5h, B9h, BDh
–
–
Register Name
Master PIC ICW1 Init. Cmd Word 1
Master PIC OCW2 Op Ctrl Word 2
Master PIC OCW3 Op Ctrl Word 3
Master PIC ICW2 Init. Cmd Word 2
Master PIC ICW3 Init. Cmd Word 3
Master PIC ICW4 Init. Cmd Word 4
Master PIC OCW1 Op Ctrl Word 1
Slave PIC ICW1 Init. Cmd Word 1
Slave PIC OCW2 Op Ctrl Word 2
Slave PIC OCW3 Op Ctrl Word 3
Slave PIC ICW2 Init. Cmd Word 2
Slave PIC ICW3 Init. Cmd Word 3
Slave PIC ICW4 Init. Cmd Word 4
Slave PIC OCW1 Op Ctrl Word 1
Master PIC Edge/Level Triggered
Slave PIC Edge/Level Triggered
Default Value
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
00h
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
00h
00h
00h
Type
WO
WO
WO
WO
WO
WO
R/W
WO
WO
WO
WO
WO
WO
R/W
R/W
R/W
Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers section
(Chapter 5.9).
372
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet