82801FB Datasheet, PDF (459/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.6 PI—Programming Interface Register (SATA–D31:F2)
12.1.6.1
When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h
Address Offset: 09h
Default Value: See bit description
Attribute: R/W, RO
Size:
8 bits
12.1.6.2
Bit
Description
7 This read-only bit is a 1 to indicate that the ICH6 supports bus master operation
6:4 Reserved. Will always return 0.
Secondary Mode Native Capable (SNC) — RO.
0 = Secondary controller only supports legacy mode.
3 1 = Secondary controller supports both legacy and native modes.
When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. When
MAP.MV is 00b, this bit reports as a 1.
Secondary Mode Native Enable (SNE) — R/W / RO. This bit determines the mode that the
secondary channel is operating in.
0 = Secondary controller operating in legacy (compatibility) mode
1 = Secondary controller operating in native PCI mode.
2
When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-only (RO).
Software is responsible for clearing this bit before entering combined mode. When MAP.MV is 00b,
this bit is read/write (R/W).
If this bit is set by software, then the PNE bit (bit 0 of this register) must also be set by software.
While in theory these bits can be programmed separately, such a configuration is not supported by
hardware.
Primary Mode Native Capable (PNC) — RO.
0 = Primary controller only supports legacy mode.
1 1 = Primary controller supports both legacy and native modes.
When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports as a 0. When
MAP.MV is 00b, this bit reports as a 1
Primary Mode Native Enable (PNE) — R/W / RO. This bit determines the mode that the primary
channel is operating in.
0 = Primary controller operating in legacy (compatibility) mode.
1 = Primary controller operating in native PCI mode.
0
When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit is read-only (RO).
Software is responsible for clearing this bit before entering combined mode. When MAP.MV is 00b,
this bit is read/write (R/W).
If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by software.
While in theory these bits can be programmed separately, such a configuration is not supported by
hardware.
When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h
Address Offset: 09h
Default Value: 00h
Attribute: RO
Size:
8 bits
Bit
Description
7:0 Interface (IF) — RO. When configured as RAID, this register becomes read only 0.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
459