82801FB Datasheet, PDF (329/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI-to-PCI Bridge Registers (D30:F0)
9.1.5
9.1.6
Bit
Description
Received Master Abort (RMA) — R/WC.
13 _{0 = No master abort received.}
1 = Set when the bridge receives a master abort status from the backbone.
Received Target Abort (RTA) — R/WC.
12 _{0 = No target abort received.}
1 = Set when the bridge receives a target abort status from the backbone.
Signaled Target Abort (STA) — R/WC.
11 _{0 = No signaled target abort}
1 = Set when the bridge generates a completion packet with target abort status on the backbone.
10:9 Reserved.
Data Parity Error Detected (DPD) — R/WC.
8
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a previous request,
and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6).
7:5 Reserved.
4 Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.
3 Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate interrupts.
2:0 Reserved
I/O Space Enable (IOSE) — R/W. Controls the response as a target for I/O cycles targeting PCI.
0 0 = Disable
0 = Enable
RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 6 (ICH6) Family Specification Update for
the value of the Revision ID Register
CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09-0Bh
Default Value: 060401h
Attribute:
Size:
RO
32 bits
Bit
Description
23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
15:8 Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI bridge.
7:0 Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is subtractive decode
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
329