82801FB Datasheet, PDF (702/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

PCI Express* Configuration Registers
19.1.43
PMCS—PCI Power Management Control and Status
Register (PCI Express—D28:F0/F1/F2/F3)
Address Offset: A4–A7h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:24
23
22
21:16
15
14:9
8
7:2
1:0
Reserved
Bus Power / Clock Control Enable (BPCE) — Reserved per PCI Express* Base Specification,
Revision 1.0a.
B2/B3 Support (B23S) — Reserved per PCI Express* Base Specification, Revision 1.0a.
Reserved
PME Status (PMES) — RO. This bit indicates a PME was received on the downstream link.
Reserved
PME Enable (PMEE) — R/W. This bit indicates PME is enabled. The root port takes no action on
this bit, but it must be R/W for some legacy operating systems to enable PME# on devices
connected to this root port.
This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which is not
asserted during a warm reset.
Reserved
Power State (PS) — R/W. This field is used both to determine the current power state of the root
port and to set a new power state. The values are:
00 = D0 state
11 = D3_HOT state
NOTE: When in the D3_HOT state, the controller’s configuration space is available, but the I/O and
memory spaces are not. Type 1 configuration cycles are also not accepted. Interrupts are
not required to be blocked as software will disable interrupts prior to placing the port into
D3_HOT. If software attempts to write a ‘10’ or ‘01’ to these bits, the write will be ignored.
702
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet