82801FB Datasheet, PDF (141/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Functional Description
Table 5-17. Interrupt Message Data Format
Bit
Description
31:16
15
14
13:12
11
10:8
7:0
Will always be 0000h.
Trigger Mode: 1 = Level, 0 = Edge. Same as the corresponding bit in the I/O Redirection Table
for that interrupt.
Delivery Status: 1 = Assert, 0 = De-assert. Only Assert messages are sent. This bit is always 1.
Will always be 00
Destination Mode: 1 = Logical. 0 = Physical. Same as the corresponding bit in the I/O
Redirection Table for that interrupt.
Delivery Mode: This is the same as the corresponding bits in the I/O Redirection Table for that
interrupt.
000 = Fixed 100 = NMI
001 = Lowest Priority 101 = INIT
010 = SMI/PMI 110 = Reserved
011 = Reserved 111 = ExtINT
Vector: This is the same as the corresponding bits in the I/O Redirection Table for that interrupt.
5.11 Serial Interrupt (D31:F0)
The ICH6 supports a serial IRQ scheme. This allows a single signal to be used to report interrupt
requests. The signal used to transmit this information is shared between the host, the ICH6, and all
peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock,
and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a
device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the
following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the
following fashion:
• S – Sample Phase. Signal driven low
• R – Recovery Phase. Signal driven high
• T – Turn-around Phase. Signal released
The ICH6 supports a message for 21 serial interrupts. These represent the 15 ISA interrupts
(IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial
IRQ protocol does not support the additional APIC interrupts (20–23).
Note:
When the IDE controller is enabled or the SATA controller is configured for legacy IDE mode,
IRQ14 and IRQ15 are are expected to behave as ISA legacy interrupts, which cannot be shared, i.e.
through the Serial Interrupt pin. If IRQ14/IRQ15 are shared with the Serial Interrupt pin then
abnormal system behavior may occur. For example, IRQ14/IRQ15 may not be detected by the
ICH6’s interrupt controller.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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