82801FB Datasheet, PDF (565/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)
Address:
Default Value:
06–07h
0280h
Attributes:RO, R/WC
Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
effect.
Bit
Description
Detected Parity Error (DPE) — R/WC.
15 _{0 = No parity error detected.}
1 = Parity error detected.
Signaled System Error (SSE) — R/WC.
14 _{0 = No system error detected.}
1 = System error detected.
13 Received Master Abort (RMA) — RO. Hardwired to 0.
12 Received Target Abort (RTA) — RO. Hardwired to 0.
Signaled Target Abort (STA) — R/WC.
11 _{0 = ICH6 did Not terminate transaction for this function with a target abort.}
1 = The function is targeted with a transaction that the Intel^® ICH6 terminates with a target abort.
DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL# assertion for
10:9 ^{positive decode.}
01 = Medium timing.
8 Data Parity Error Detected (DPED) — RO. Hardwired to 0.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
4
Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list structures in
this function
3
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent from
the state of the Interrupt Enable bit in the PCI Command register.
2:0 Reserved
15.1.5
RID—Revision Identification Register (SMBus—D31:F3)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 6 (ICH6) Family Specification Update for
the value of the Revision ID Register
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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