82801FB Datasheet, PDF (498/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
Bit
Description
Interlock Switch Attached to Port (ISP) — R/WO. When interlock switches are supported in the
platform (CAP.SIS [ABAR+00h:bit 28] set), this indicates whether this particular port has an interlock
switch attached. This bit can be used by system software to enable such features as aggressive
power management, as disconnects can always be detected regardless of PHY state with an
19 ^{interlock switch. When this bit is set, it is expected that HPCP (bit 18) in this register is also set.}
The ICH6 takes no action on the state of this bit – it is for system software only. For example, if this
bit is cleared, and an interlock switch toggles, the ICH6 still treats it as a proper interlock switch
event.
Note that these bits are not reset on a HBA reset.
Hot Plug Capable Port (HPCP) — R/WO.
0 = Port is not capable of Hot-Plug.
1 = Port is Hot-Plug capable.
This indicates whether the platform exposes this port to a device which can be Hot-Plugged. SATA
18 ^{by definition is hot-pluggable, but not all platforms are constructed to allow the device to be removed}
(it may be screwed into the chassis, for example). This bit can be used by system software to
indicate a feature such as "eject device" to the end-user. The ICH6 takes no action on the state of
this bit - it is for system software only. For example, if this bit is cleared, and a Hot-Plug event
occurs, the ICH6 still treats it as a proper Hot-Plug event.
Note that these bits are not reset on a HBA reset.
Port Multiplier Attached (PMA) — RO / R/W. When this bit is set, a port multiplier is attached to the
ICH6 for this port. When cleared, a port multiplier is not attached to this port.
17
This bit is RO 0 when CAP.PMS (offset ABAR+00h:bit 17) = 0 and R/W when CAP.PMS = 1.
NOTE: Port Multiplier not supported by ICH6.
16
Port Multipler FIS Based Switching Enable (PMFSE) — RO. The ICH6 does not support FIS-based
switching.
Controller Running (CR) — RO. When this bit is set, the DMA engines for a port are running. See
15 section 5.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and cleared by
the ICH6.
FIS Receive Running (FR) — RO. When set, the FIS Receive DMA engine for the port is running.
14 See section 12.2.2 of the Serial ATA AHCI Specification for details on when this bit is set and
cleared by the ICH6.
Interlock Switch State (ISS) — RO. For systems that support interlock switches (via CAP.SIS
[ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP in this register), this bit indicates
the current state of the interlock switch. A 0 indicates the switch is closed, and a 1 indicates the
13 _{switch is opened.}
For systems that do not support interlock switches, or if an interlock switch is not attached to this
port, this bit reports 0.
Current Command Slot (CCS) — RO. This field indicates the current command slot the ICH6 is
processing. This field is valid when the ST bit is set in this register, and is constantly updated by the
ICH6. This field can be updated as soon as the ICH6 recognizes an active command slot, or at some
12:8 ^{point soon after when it begins processing the command.}
This field is used by software to determine the current command issue location of the ICH6. In
queued mode, software shall not use this field, as its value does not represent the current command
being executed. Software shall only use PxCI and PxSACT when running queued commands.
7:5 Reserved
FIS Receive Enable (FRE) — R/W. When set, the ICH6 may post received FISes into the FIS
receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU (ABAR+10Ch/18Ch/
20Ch/28Ch). When cleared, received FISes are not accepted by the ICH6, except for the first D2H
4 ^{(device-to-host) register FIS after the initialization sequence.}
System software must not set this bit until PxFB (PxFBU) have been programmed with a valid
pointer to the FIS receive area, and if software wishes to move the base, this bit must first be
cleared, and software must wait for the FR bit (bit 14) in this register to be cleared.
3 Port Selector Activate (PSA) — RO. Port Selector not supported. Defaults to 0.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet