82801FB Datasheet, PDF (747/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Electrical Characteristics
Table 22-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 1 of 2)
Sym
Parameter1
Mode 0
(ns)
Min Max
Mode 1
(ns)
Min Max
Mode 2
(ns)
Min Max
Measuring
Location
Figure
t80 Sustained Cycle Time (T2cyctyp)
240
160
120
Sender
Connector
t81 Cycle Time (Tcyc)
End
112 – 73 – 54 – Recipient 22-10
Connector
t82 Two Cycle Time (T2cyc)
230
–
153
–
115
–
Sender
Connector
22-10
t83a Data Setup Time (Tds)
15 – 10 –
7
–
Recipient
Connector
22-10
Recipient IC data setup time (from
t83b data valid until STROBE edge)
14.7 – 9.7 – 6.8 – ICH6 ball
(see Note 2) (Tdsic)
t84a Data Hold Time (Tdh)
5
–
5
–
5
–
Recipient
Connector
22-10
Recipient IC data hold time (from
t84b
STROBE edge until data may
become invalid) (see Note 2)
4.8 – 4.8 – 4.8 – ICH6 ball
(Tdhic)
t85a Data Valid Setup Time (Tdvs)
70
–
48
–
31
–
Sender
Connector
22-10
Sender IC data valid setup time
t85b (from data valid until STROBE
edge) (see Note 2) (Tdvsic)
72.9 – 50.9 – 33.9 – ICH6 ball
t86a Data Valid Hold Time (Tdvh)
6.2
–
6.2
–
6.2
–
Sender
Connector
22-10
Sender IC data valid hold time
t86b
(from STROBE edge until data
may become invalid) (see Note 2)
9
–
9
–
9
– ICH6 ball
(Tdvhic)
t87 Limited Interlock Time (Tli)
0 150 0 150 0 150 Note 2 22-12
t88 Interlock Time w/ Minimum (Tmli)
20
–
20
–
20
–
Host
Connector
22-12
t89 Envelope Time (Tenv)
20
70
20
70
20
70
Host
Connector
22-9
t90 Ready to Pause Time (Trp)
160
–
125
–
100
–
Recipient
Connector
22-11
t91 DMACK setup/hold Time (Tack)
20
–
20
–
20
–
Host
22-9,
Connector 22-12
t92a
CRC Word Setup Time at Host
(Tcvs)
70
–
48
–
31
–
Host
Connector
CRC word valid hold time at
t92b
sender (from DMACK# negation
until CRC may become invalid)
(see Note 2) (Tcvh)
6.2
–
6.2
–
6.2
–
Host
Connector
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
747