82801FB Datasheet, PDF (457/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.1.2
12.1.3
DID—Device Identification Register (SATA—D31:F2)
Offset Address:
Default Value:
Lockable:
02–03h
ICH6: 2651h
ICH6R: 2652h
ICH6-M: 2653h
No
Attribute:
Size:
Power Well:
RO
16 bit
Core
Bit
Description
15:0 Device ID — RO. This is a 16-bit value assigned to the ICH6 SATA controller.
PCICMD—PCI Command Register (SATA–D31:F2)
Address Offset: 04h–05h
Default Value: 0000h
Attribute: RO, R/W
Size:
16 bits
Bit
Description
15:11
10
9
8
7
6
5
4
3
2
Reserved
Interrupt Disable — R/W. This bit disables pin-based INTx# interrupts. This bit has no effect on MSI
operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled.
1 = Internal INTx# messages will not be generated.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. This bit controls the ICH6’s ability to act as a PCI master for IDE
Bus Master transfers. This bit does not impact the generation of completions for split transaction
commands.
Memory Space Enable (MSE) — R/W / RO. This bit controls access to the SATA controller’s target
memory space (for AHCI). (ICH6-M/ICH6R only)
1
NOTE: When MAP.MV (offset 90:bits 1:0) is not 00h, this register is Read Only (RO). Software is
responsible for clearing this bit before entering combined mode.
For ICH6, this bit is RO ‘0’, unless the SCRAE bit (offset 94h:bit 9) is set.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
0
Bus Master I/O registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
457