82801FB Datasheet, PDF (555/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

EHCI Controller Registers (D29:F7)
14.2.2.7
ASYNCLISTADDR—Current Asynchronous List Address
Register
Offset:
Default Value:
MEM_BASE + 38–3Bh
00000000h
Attribute: R/W
Size:
32 bits
This 32-bit register contains the address of the next asynchronous queue head to be executed. Since
the ICH6 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing
Capability field in the HCCPARAMS register) (offset 08h, bit 0), then the most significant 32 bits
of every control data structure address comes from the CTRLDSSEGMENT register (offset 08h).
Bits [4:0] of this register cannot be modified by system software and will always return 0’s when
read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte
aligned.
14.2.2.8
Bit
Description
31:5
Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals [31:5],
respectively. This field may only reference a Queue Head (QH).
4:0 Reserved. These bits are reserved and their value has no effect on operation.
CONFIGFLAG—Configure Flag Register
Offset:
Default Value:
MEM_BASE + 60–63h
00000000h
Attribute: R/W
Size:
32 bits
This register is in the suspend power well. It is only reset by hardware when the suspend power is
initially applied or in response to a host controller reset.
Bit
Description
31:1 Reserved. Read from this field will always return 0.
Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process of
configuring the Host controller. This bit controls the default port-routing control logic. Bit values and
0 ^{side-effects are listed below. See section 4 of the EHCI specification for operation details.}
0 = Port routing control logic default-routes each port to the classic host controllers (default).
1 = Port routing control logic default-routes all ports to this host controller.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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