82801FB Datasheet, PDF (274/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
7.1.53
7.1.54
HPTC—High Precision Timer Configuration Register
Offset Address: 3404–3407h
Default Value: 00000000h
Attribute:
Size:
R/W
32-bit
Bit
Description
31:8 Reserved
Address Enable (AE) — R/W.
7
0 = Address disabled.
1 = The Intel^® ICH6 will decode the High Precision Timer memory address range selected by bits
1:0 below.
6:2 Reserved
Address Select (AS) — R/W. This 2-bit field selects 1 of 4 possible memory address ranges for
the High Precision Timer functionality. The encodings are:
00 = FED0_0000h–FED0_03FFh
1:0
01 = FED0_1000h–FED0_13FFh
10 = FED0_2000h–FED0_23FFh
11 = FED0_3000h–FED0_33FFh
GCS—General Control and Status Register
Offset Address:
Default Value:
3410–3413h
0000000yh y=(00x0x000b)
Attribute:
Size:
R/W, R/WLO
32-bit
Bit
Description
31:10 Reserved
Server Error Reporting Mode (SERM) — R/W.
0 = The Intel^® ICH6 is the final target of all errors. The (G)MCH sends a messages to the ICH for
the purpose of generating NMI.
9
1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this mode, if the
ICH6 detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends
a message to the (G)MCH. If the ICH6 receives an ERR_* message from the downstream
port, it sends that message to the (G)MCH.
8
Reserved
7
(Mobile)
Mobile IDE Configuration Lock Down (MICLD) — R/WLO.
0 = Disabled.
1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system reset occurs.
This prevents rogue software from changing the default state of the PATA pins during boot
after BIOS configures them. This bit is write once, and is cleared by system reset and when
returning from the S3/S4/S5 states.
7
Reserved
(Desktop)
FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor break event
indication.
6
0 = Disabled.
1 = The ICH6 examines FERR# during a C2, C3, or C4 state as a break event.
See Chapter 5.14.5 for a functional description.
274
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet