82801FB Datasheet, PDF (577/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SMBus Controller Registers (D31:F3)
15.2.14 SMBus_PIN_CTL—SMBus Pin Control Register
(SMBus—D31:F3)
Register Offset: SMBASE + 0Fh
Default Value: See below
Attribute:
Size:
R/W, RO
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit
Description
7:3 Reserved
SMBCLK_CTL — R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of the pin.
2
0 = ICH6 drives the SMBCLK pin low, independent of what the other SMB logic would otherwise
indicate for the SMBCLK pin. (Default)
SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent on an
external signal level. This pin returns the value on the SMBDATA pin. This allows software to read
1 ^{the current state of the pin.}
0 = Low
1 = High
SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMBCLK pin. This allows software to read the current
0 ^{state of the pin.}
0 = Low
1 = High
15.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3)
Register Offset: SMBASE + 10h
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
Note: This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll
this register until a write takes effect before assuming that a write has completed internally.
Bit
Description
7:1 Reserved
HOST_NOTIFY_STS — R/WC. The ICH6 sets this bit to a 1 when it has completely received a
successful Host Notify Command on the SMLink pins. Software reads this bit to determine that the
source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this
0 bit after reading any information needed from the Notify address and data registers by writing a 1 to
this bit. Note that the ICH6 will allow the Notify Address and Data registers to be over-written once
this bit has been cleared. When this bit is 1, the ICH6 will NACK the first byte (host address) of any
new “Host Notify” commands on the SMLink. Writing a 0 to this bit has no effect.
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
577