82801FB Datasheet, PDF (450/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

IDE Controller Registers (D31:F1)
11.1.25
IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)
Address Offset: 54h
Default Value: 00000000h
Attribute: R/W
Size:
32 bits
Bit
Description
31:24
23:20
19:18
17:16
15:14
13
12
11:8
7
6
5
4
3:2
1
0
Reserved
Miscellaneous Scratchpad (MS) — R/W. Previously defined as a scratchpad bit to indicate to a
driver that ATA-100 is supported. This is not used by software as all they needed to know was
located in bits 7:4. See the definition of those bits.
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no
functionality in the ICH6.
SIG_MODE — R/W. These bits are used to control mode of the IDE signal pins for swap bay
support.
If the PRS bit (Chipset Configuration Registers:Offset 3414h:bit 1) is 1, the reset states of bits 17:16
will be 01 (tri-state) instead of 00 (normal).
00 = Normal (Enabled)
01 = Tri-state (Disabled)
10 = Drive low (Disabled)
11 = Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no
functionality in the ICH6.
Fast Primary Drive 1 Base Clock (FAST_PCB1) — R/W. This bit is used in conjunction with the
PCT1 bits to enable/disable Ultra ATA/100 timings for the Primary Slave drive.
0 = Disable Ultra ATA/100 timing for the Primary Slave drive.
1 = Enable Ultra ATA/100 timing for the Primary Slave drive (overrides bit 1 in this register).
Fast Primary Drive 0 Base Clock (FAST_PCB0) — R/W. This bit is used in conjunction with the
PCT0 bits to enable/disable Ultra ATA/100 timings for the Primary Master drive.
0 = Disable Ultra ATA/100 timing for the Primary Master drive.
1 = Enable Ultra ATA/100 timing for the Primary Master drive (overrides bit 0 in this register).
Reserved
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no
functionality in the ICH6.
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no
functionality in the ICH6.
Primary Slave Channel Cable Reporting — R/W. BIOS should program this bit to tell the IDE
driver which cable is plugged into the channel.
0 = 40 conductor cable is present.
1 = 80 conductor cable is present.
Primary Master Channel Cable Reporting — R/W. Same description as bit 5
No Operation (NOP) — R/W. These bits are read/write for legacy software compatibility, but have no
functionality in the ICH6.
Primary Drive 1 Base Clock (PCB1) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
Primary Drive 0 Base Clock (PCB0) — R/W.
0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet