82801FB Datasheet, PDF (249/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

Chipset Configuration Registers
Table 7-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 3 of 3)
Offset
Mnemonic
Register Name
Default
Type
341C–341Fh
3E08–3E09h
3E0Eh
3E48–3E49h
3E4Eh
CG
CSIR1
CSIR3
CSIR2
CSIR4
Clock Gating
Chipset Initialization Register 1
Chipset Initialization Register 4
Chipset Initialization Register 2
Chipset Initialization Register 4
00000000h
0000h
00h
0000h
00h
R/W, RO
R/W
R/W
R/W
R/W
7.1.1
7.1.2
VCH—Virtual Channel Capability Header Register
Offset Address: 0000–0003h
Default Value: 10010002h
Attribute:
Size:
RO
32-bit
Bit
31:20
19:16
15:0
Description
Next Capability Offset (NCO) — RO. This field indicates the next item in the list.
Capability Version (CV) — RO. This field indicates support as a version 1 capability structure.
Capability ID (CID) — RO. This field indicates this is the Virtual Channel capability item.
VCAP1—Virtual Channel Capability #1 Register
Offset Address: 0004–0007h
Default Value: 00000801h
Attribute:
Size:
RO
32-bit
Bit
31:12
11:10
9:8
7
6:4
3:0
Description
Reserved
Port Arbitration Table Entry Size (PATS) — RO. This field indicates the size of the port arbitration
table is 4 bits (to allow up to 8 ports).
Reference Clock (RC) — RO. Fixed at 100 ns.
Reserved
Low Priority Extended VC Count (LPEVC) — RO. This field indicates that there are no additional
VCs of low priority with extended capabilities.
Reserved
Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet
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