82801FB Datasheet, PDF (488/786 Pages) Intel Corporation – Intel I/O Controller Hub 6 (ICH6) Family

SATA Controller Registers (D31:F2)
12.3.1.2
GHC—Global ICH6 Control Register (D31:F2)
Address Offset: ABAR + 04h–07h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
AHCI Enable (AE) — R/W. When set, this bit indicates that an AHCI driver is loaded and the
controller will be talked to via AHCI mechanisms. This can be used by an ICH6 that supports both
legacy mechanisms (such as SFF-8038i) and AHCI to know when the controller will not be talked to
as legacy.
31 _{When set, software will only talk to the ICH6 using AHCI. The ICH6 will not have to allow command}
processing via both AHCI and legacy mechanisms. When cleared, software will only talk to the ICH6
using legacy mechanisms.
Software shall set this bit to 1 before accessing other AHCI registers.
30:2 Reserved. Returns 0.
Interrupt Enable (IE) — R/W. This global bit enables interrupts from the ICH6.
1 _{0 = All interrupt sources from all ports are disabled.}
1 = Interrupts are allowed from the AHCI controller.
HBA Reset (HR) — R/W. Resets ICH6 AHCI controller.
0 = No effect
1 = When set by SW, this bit causes an internal reset of the ICH6 AHCI controller. All state
0
machines that relate to data transfers and queuing return to an idle condition, and all ports are
re-initialized via COMRESET.
NOTE: For further details, consult section 12.3.3 of the Serial ATA Advanced Host Controller
Interface specification.
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Intel^® I/O Controller Hub 6 (ICH6) Family Datasheet